In modern computer system design it is common for multiple devices to be coupled to a common communication bus. Moreover, it is also common for more than one of these devices to possess the capability to act as a bus master which controls the transfer of data, control and address signals between itself and another device over the common communication bus. In such computer systems it is therefore necessary to implement an arbitration scheme to determine the order in which these multiple bus master devices may control the common bus. The arbitration scheme is utilized during situations in which two or more of the bus master devices simultaneously seek to control the common bus.
Arbitration schemes are often implemented via a separate arbitration control circuit component which is coupled to each of the devices which can control the common bus. However, the use of a separate arbitration control component adds to the I/O requirements of the bus master devices as well as the wiring complexity of the system. Consequently, the external arbitration control component limits the number of devices that may be used in a given computer system. Furthermore, inter-device transactions with the separate arbitration control component are inherently slower than on-device transactions. Thus, it is advantageous to include the arbitration control circuitry on a bus master device.
In systems comprising multiple bus master devices it may be further desirable to utilize common circuitry for each of the bus master devices. The use of a single part number for the bus master devices may result in significant cost savings for the system. In a system comprising multiple bus master devices it may be advantageous to include bus arbitration control circuitry on each of the devices such that the bus master--arbitration control devices represent a single part number in the system design.
Accordingly, recent designs have incorporated arbitration control circuitry onto devices capable of controlling the common bus. For example, U.S. Pat. No. 4,745,548 to Blahut (issued May 17, 1988), teaches the inclusion of a separate self-contained arbitration request circuit and a separate arbitration resolution circuit as a part of each of the chips that require access to a common data bus.
In a system including multiple bus master devices having built-in arbitration control circuitry, a mechanism must be provided to perform arbitration between the multiple bus master devices with the included arbitration circuits. In certain systems, such as the aforementioned system disclosed in the patent to Blahut, as well as the system described in U.S. Pat. No. 4,482,950 to Dshkhunian et al. (issued Nov. 13, 1988) a distributed arbitration scheme is implemented wherein each of the on-chip arbitration circuits actively participates in determining which bus master will control the common bus.
In distributed arbitration schemes, each of the multiple bus master devices is typically assigned a priority which reflects the sequence in which each of the multiple bus master devices may control the bus. A bus master device having a high priority will take precedence over a bus master device having a low priority when each of the devices simultaneously requests control of the common bus. Priority may be determined by the position at which a particular bus master device attaches to the common bus. In the distributed arbitration scheme described in U.S. Pat. No. 5,408,129 to Farmwald et al. (issued Apr. 18, 1995), each device on the bus is assigned a unique device ID number. When a collision between bus master requests to control the common bus occurs, each bus master device seeking to control the bus drives a single BusData line during a single bus cycle corresponding to its assigned master ID number, and a fixed priority scheme is implemented to sequence the requests in a bus arbitration queue maintained by at least one device. Further bus master requests are disabled until the queue is cleared.
Distributed arbitration designs are not the optimum means for performing bus arbitration in all systems utilizing a commonly accessed bus. Typically the distributed arbitration design is inflexible and it is difficult to affect a modification in priority assignments. Moreover, priority assignments may lead to the "starvation" of a lower priority device. Consequently, such prioritization schemes mandate a prioritization of the operations to be performed by each of the bus masters, to ensure that low priority devices which control the bus less frequently than high priority devices are not responsible for performing the most important operations over the common data bus. Furthermore, in priority schemes such as the scheme disclosed in the patent to Farmwald et al., bus cycles are devoted to the resolution of conflicting bus master requests thereby reducing the bandwidth of the common data bus.
Accordingly, certain designs for systems implementing a commonly accessed bus dictate the implementation of a single point arbitration scheme incorporating multiple bus master devices including arbitration control circuitry. Systems including a commonly accessed bus in which the arbitration is performed by a single arbitration control circuit on one of the bus master devices including arbitration control circuitry are typically implemented by providing additional I/O on each of the bus master devices. The additional I/O serves to enable an arbitration control circuit on a single bus master device, while disabling each of the arbitration control circuits on the other bus master devices. However, such an implementation adds I/O to each of the bus master devices, and thus conflicts with the original motivation for combining the bus master devices with the arbitration control circuitry.